1. Field of the Invention
The invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device repairing a bad column by using a redundant memory.
2. Description of Related Art
For semiconductor memories such as flash memory, dynamic random access memory (DRAM), etc., it is a challenge to manufacture a memory element without a failure or a defect due to the continuous increase of the degree of integration. Thus, a redundancy scheme exists to repair apparent physical defect of a memory element occurring during a manufacturing process. For example, a redundancy scheme may include an address conversion circuit and a redundant memory region. Wherein the address conversion circuit converts an address of the memory element having the physical defect to an address of a memory element in the redundant memory region. Accordingly, the redundant memory region serves to repair the defective memory element. The address information of the defective memory and the memory element in the redundant memory region is stored in a fuse read only memory (ROM) or a register during a test for the memory chip or when the memory chip is shipped. In addition, when the address of the defective memory element is input and the address is detected, accessing of the defective memory element is forbidden. Instead, the memory element in the redundant memory region is accessed. Thus, superficially, the defective memory element does not seem to exist. By adopting such redundancy scheme (e.g., Japan Patent Publication No. 2000-311496 and Japan Patent Publication No. 2002-288993), even though some memory elements are defective, the memory may still be considered as a non-defective product. The yield rate is thus increased, and the cost of the memory is reduced.
An NAND type flash memory has a memory array. The memory array has NAND strings each including a plurality of memory cells that are serially connected. In addition, one page of data are read from or programmed (written) to the memory array as a unit through a page buffer/sense circuit. Besides, during reading and programming operations with page as a unit, to suppress interference between adjacent bit lines as much as possible, a method of dividing a page into an odd page and an even page is adopted. In the flash memory, when a column of the memory array has a failure (e.g., a short circuit or an open circuit), the even column and the odd column of the column including the failure are set as a set of bad columns, and the set of bad columns are repaired by using a set of redundant columns in the redundant memory region.
FIGS. 1(A) and 1(B) are views illustrating a conventional method for repairing a bad column of a flash memory. As shown in FIG. 1(A), the memory array has a column address Col_0 having an even column e and an odd column o, a column address Col_1 having an even column e and an odd column o, and a column address Col_2 having an even column e and an odd column o. When there is a failure F (e.g., short circuit) between the even column e and the odd column o in the column address Col_2, a set of an even column e and an odd column o in a redundant column address Red_0 in the redundant memory region is used to repair the set of the even column e and the odd column o of the column address Col_2 containing failure.
Alternatively, as shown in FIG. 1(B), when the failure F crosses the odd column o of the column address Col_1 and the even column e of the column address Col_2, the set of the even column e and the odd column o in the column address Col_1 containing failure and the set of the even column e and the odd column o in the column address Col_2 containing failure, are repaired by using a set of the even column e and the odd column o in the redundant column address Red_0 and a set of an even column e and an odd column o in a redundant column address Red_1.
However, in the two sets of bad columns shown in FIG. 1(B), the even column e in the column address Col_1 and the odd column o in the column address Col_2 are actually not defective and do not need to be repaired. Since the even column e in the column address Col_1 and the odd column o in the column address Col_2 that are not defective are also repaired, there is a waste in the repairing process of the redundant memory region, so the repair efficiency is lowered, and more redundant memory is consequently needed, thereby making the cost of the flash memory increase.